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19-2970; Rev 3; 1/09
KIT ATION EVALU LE B AVAILA
WCDMA Quasi-Direct Modulator with VGA and PA Driver
General Description Features
o 5% EVM for POUT = +6dBm o 1920MHz to 1980MHz Operation o +2.7V to +3.3V Single-Supply Operation o +6dBm Output Power at 72mA o 81dB Minimum Automatic Gain-Control (AGC) Range o Automatic ICC Throttle Back for Optimal Power Consumption o No IF SAW Filter Necessary o On-Chip RF PLL, with Fully Monolithic VCO o Ultra-Low External Component Count
MAX2395
The MAX2395 fully monolithic quasi-direct modulator IC is designed for use in WCDMA/UMTS transmitters. The quasi-direct modulation architecture reduces system cost, component count, and board space compared to transmitters using an IF SAW filter with IF VCO and IF synthesizer blocks. The MAX2395 includes I/Q baseband filters, an IF I/Q modulator with VGA, a fully monolithic VCO with PLL, an upconverter mixer, an RF VGA, and a power amplifier (PA) driver. The use of the quasi-direct modulator scheme ensures 5% (typ) EVM and a 30dB (min) carrier suppression. The RF VGA and IF VGA provide a nominal 90dB of output power control. No external local oscillators are required, enabling efficient implementation of variable duplex offset systems. The PLL is programmed by loading data on the SPITM/ MICROWIRETM-compatible 3-wire serial bus. The IC operates from a single +2.7V to +3.3V supply. The devices are available in space-saving 28-pin QFN and thin QFN exposed-pad packages (5mm x 5mm).
Ordering Information
PART MAX2395EGI MAX2395ETI MAX2395ETI+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 QFN-EP* 28 TQFN-EP* 28 TQFN-EP*
Applications
WCDMA Phones UMTS/EDGE Phones W-TDD Phones
*EP = Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration/ Functional Diagram
VTUNE
22 21 20 RF INTEGER-N PLL 19 18 17 90 MAX2395 16 REF GND_VCO VCC_VCO RFCP VCC_CP
SDATA
SCLK
N.C.
N.C.
24
+
N.C. POUT 1 2 3 4 5 6
28
27 SERIAL BUS
26
25
23
VCC_PA BIAS_SET VGC
LO GEN
BVP
CS
SPI is a trademark of Motorola, Inc.
0 VCC_PLL
MICROWIRE is a trademark of National Semiconductor Corp.
VCC_IF VCC_BB
7 8 9 10 11 12 13 14
15
LD
IDLE
SHDN
I+
I-
Q+
Q-
________________________________________________________________ Maxim Integrated Products
N.C.
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +3.6V All Other Pins to GND..................................-0.3V to VCC_ + 0.3V I_, Q_, REF to GND..............................................................1VP-P Digital Input Current .........................................................10mA Continuous Power Dissipation (TA = +70C) 28-Pin QFN (derate 20.8mW/C above +70C) .........1667mW 28-Pin TQFN (derate 21.3mW/C above +70C) .......1702mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.3V, RBIAS = 12k, TA = -40C to +85C. Typical values are at VCC = +2.85V and TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Supply Voltage Range VVGC = 0.35V Operating Supply Current POUT = 0dBm POUT = +6dBm Idle Current Shutdown Current VGC Input Current VGC Input Current During Shutdown Gain-Control Voltage Range Lock Indicator High--Leakage Current Lock Indicator Low--Sink Voltage SHDN Input Logic-High, VDH SHDN Input Logic-Low SHDN Input Resistance Digital Input Logic-High, VIH Digital Input Logic-Low, VIL Digital Control Pin Input Current I/Q Input Leakage Current I/Q DC Common-Mode Voltage Resistance to ground All digital input pins including IDLE, SDATA, SCLK, and CS (Note 3) All digital input pins including IDLE, SDATA, SCLK, and CS (Note 3) IDLE, SDATA, SCLK, and CS PLL locked, VLD = VCC PLL unlocked, sinking 100A 1.5 0 50 0.7 x VDH 0 -10 -10 1.35 1.45 VCC 0.3 x VDH +10 +10 1.65 SHDN = VIL 0.35 IDLE = VIL SHDN = 0 -10 IDLE_PRG = 0 IDLE_PRG = 1 CONDITIONS MIN 2.7 TYP 2.85 46 67 72 16 19 0.5 MAX 3.3 60 82 90 21 27 10 +10 1 2.20 4 0.4 VCC 0.5 A A A V A V V V k V V A A V mA UNITS V
2
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WCDMA Quasi-Direct Modulator with VGA and PA Driver
AC ELECTRICAL CHARACTERISTICS
MAX2395 EV kit, VCC = +2.7V to +3.3V, RBIAS = 12k, VVGC adjusted to obtain maximum rated output power, and TA = -40C to +85C. I/Q inputs driven differentially with low- impedance source based on 3GPP UpLink reference measurement channel (12.2kbps), envelope level 1VP-P. Typical values are at VCC = +2.85V and TA = +25C, unless otherwise noted. See Tables 1 and 3 for register settings.) (Note 2)
PARAMETER CASCADED RF SPECIFICATIONS RF Frequency Range (Notes 4, 6) Maximum Output Power (Note 6) Out-of-Band Emissions (Note 6) Adjacent Channel Power Ratio, ACPR1 (Notes 5, 6) Alternate Channel Power Ratio, ACPR2 (Notes 5, 6) Output Noise Power Density (Note 6) Minimum Output Power Carrier Suppression Sideband Suppression EVM (Note 6) Including BB filter, POUT = +6dBm Including BB filter, POUT = -44dBm I/Q MODULATION BASEBAND INPUTS Passband Amplitude Ripple Baseband Selectivity INTEGER-N RF PLL Main PLL Integer Division Ratios Reference Frequency Range Input Frequency for Reference Frequency Doubler Reference-Divider Ratio Charge-Pump Nominal Currents (Sink or Source) Charge-Pump Leakage Current OPCTRL register bit 7 = 1 9-bit register Locked, RCP1/RCP0 = 0 1, VCC/2 Locked, RCP1/RCP0 = 1 1, VCC/2 1200 2000 16-bit register (64/65 dual-modulus prescaler) 4032 8 13 80 1500 2500 9750 19.2 65,535 40 16 511 1800 3000 20 A nA MHz MHz DC to 2MHz (Notes 6, 7) Relative to passband At 8.08MHz At 13.44MHz -0.3 8 25 35 50 +0.4 dB dB VGC set for maximum output power while meeting ACPR1, ACPR2, out-of-band emissions, and output noise density specifications At f = 1575MHz At RF + 2 x IF (image) f = 5MHz/3.84MHz BW f = 10MHz/3.84MHz BW POUT = +6dBm at 1920MHz, noise measured at 1880MHz POUT = +6dBm at 1980MHz, noise measured at 2110MHz VVGC = 0.35V 30 32 5 8.6 7.5 14.6 POUT > 0dBm and TA > 0C POUT 0dBm and TA 0C 1920 1950 1980 MHz CONDITIONS MIN TYP MAX UNITS
MAX2395
6 -31 -13 -48 -45 -60 -140 -146 -85 -24 -8.5 -45 -43 -57 -137
dBm
dBc dBc dBc dBc/Hz
-143 -78 dBm dB dB %RMS
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WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
AC ELECTRICAL CHARACTERISTICS (continued)
MAX2395 EV kit, VCC = +2.7V to +3.3V, RBIAS = 12k, VVGC adjusted to obtain maximum rated output power, and TA = -40C to +85C. I/Q inputs driven differentially with low- impedance source based on 3GPP UpLink reference measurement channel (12.2kbps), envelope level 1VP-P. Typical values are at VCC = +2.85V and TA = +25C, unless otherwise noted. See Tables 1 and 3 for register settings.) (Note 2)
PARAMETER ON-CHIP VCO Phase Noise Supply Pushing RF VCO Pulling 3-WIRE SERIAL BUS INTERFACE Data to Clock Setup, tCS Data to Clock Hold Time, tCH Clock Pulse-Width High, tCWH Clock Pulse-Width Low, tCWL Clock to Load Enable/Setup Time, tES Clock Frequency Figure 1 (Note 6) Figure 1 (Note 6) Figure 1 (Note 6) Figure 1 (Note 6) Figure 1 (Note 6) (Note 6) 20 10 20 20 20 20 ns ns ns ns ns MHz At 3MHz offset, measured at the center of the RF band (Note 6) Supply stepped from +2.7V to +3.3V, with on-chip voltage regulator When switching from IDLE mode to active Tx mode -130 0.15 0.1 -128 dBc/Hz MHz/V MHzP-P CONDITIONS MIN TYP MAX UNITS
Note 1: The following parameters are characterized using the register settings below.
Table 1. Characterization Register Settings
REGISTER RFR OPCTRL SETTINGS 4050 hex (80 dec for /R) 3B7D hex ADDRESS 0000b 0100b FUNCTION Reference-divider register Operational control settings
Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
Guaranteed at TA = +25C and TA = +85C by production test, and guaranteed by design and characterization at TA = -40C. VDH is the high voltage applied to the shutdown pin. Output power, linearity, noise power, and LO leakage specifications are met over this frequency range. Specifications valid for all output power levels, unless limited by thermal noise at lower output power levels. Guaranteed by design and characterization. Tested at 1MHz and 2MHz in the passband.
4
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WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
Typical Operating Characteristics
(VCC = +2.85V, fRF = 1950MHz, MPL = 1, and TA = +25C, unless otherwise noted.)
POUT ACPR1 vs. VVGC
MAX2395 toc01 MAX2395 toc02
EVM vs. POUT
10 9 8 TA = -40C 7 6 5 4 -30 -26 -22 -18 -14 -10 POUT (dBm) -6 -2 2 6 TA = +85C TA = +25C 20 10 POUT (dBm), ACPR (dBc) 0 -10 -20 -30 -40 -50 -60 1.5 1.6 TA = -40C
OUTPUT SPECTRUM vs. FREQUENCY
WANTED SIGNAL, 0dB RF IMAGE, 15dB RF LO-3IF, RF LO-2IF, -32dB -35dB RF LO, -42dB 0 OUTPUT SPECTRUM (dBm) -10 -20 -30 -40 -50 -60 -70 -80 -90
MAX2395 toc03 MAX2395 toc09 MAX2395 toc06
10
EVM (%RMS)
TA = +85C TA = +25C
1.7
1.8
1.9
2.0
2.1
2.2
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 FREQUENCY (GHz)
VVGC (V)
OUTPUT NOISE DENSITY vs. VVGC
MAX2395 toc04
ICC vs. VVGC
100 90 80 ICC (mA) TA = +85C VCC = 2.7V TO 3.3V, INPUT APPLIED
MAX2395 toc05
BASEBAND FILTER REPSONSE
10 0 FILTER RESPONSE (dB) -10 -20 -30 -40 -50
OUTPUT POWER NOISE DENSITY (dBm/Hz)
-130 -132 -134 -136 -138 -140 -142 -144 -146 -148 -150 -152 -154
110
fRF = 1922.4MHz TA = +25C
TA = -40C f = 2112.4MHz TA = +85C f = 1880MHz 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
70 60 50 40 30 20
TA = +25C TA = -40C -60 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 VVGC (V) 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz)
VVGC (V)
CARRIER AND SIDEBAND SUPPRESSION vs. POUT
CARRIER AND SIDEBAND SUPPRESSION (dBc) CARRIER 50 40 30 20 10 0 -74 -64 -54 -44 -34 -24 -14 -4 6 POUT (dBm) SIDEBAND
MAX2395 toc07
VGC SLOPE LINEARITY vs. POUT
65 60 55 50 45 40 35 30 -74 -64 -54 -44 -34 -24 -14 -4 6 POUT (dBm) TA = -40C -20 -25 0 TA = +25C FREQUENCY (kHz) SLOPE (dB/V) TA = +85C
MAX2395 toc08
FREQUENCY SETTLING TIME
10 5 0 -5 -10 -15 FROM 1920MHz TO 1980MHz FROM IDLE FROM SHDN
60
70
100 200 300 400 500 600 700 800 900 TIME (s)
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WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
Pin Description
PIN 1 2 NAME N.C. POUT Connect to RF GND on PCB Transmitter Output. This is an open-collector output and requires a pullup inductor to the supply voltage. This pullup inductor can be part of the output matching network and can be connected directly to the battery. Supply for the PA Driver. This pin must be bypassed with a capacitor to system ground as close to the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). Bias-Setting Pin. The DC voltage at this pin is a bandgap voltage. For nominal bias, connect a 12k resistor to ground. The value of this resistor can be adjusted to alter current consumption, linearity, and noise performance of the RF output. Gain-Control Pin. Analog input pin controls both the IF VGA and RF VGA gain. When not driven, the voltage on this pin is typically +1.5V. An RC filter on this pin must be used to filter out DAC noise or the PDM clock. Supply for IF Section. Bypass to system ground with a capacitor as close to the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). Supply for Baseband Section. Bypass to system ground with a capacitor as close to the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). Idle CMOS Digital Input. Drive LOW to place the device in WCDMA compressed mode (VCO and PLL are ON; all others are OFF). A small RC lowpass filter can be used to minimize the effect of external digital noise. Shutdown CMOS Digital Input. Drive LOW to place the device in shutdown (everything OFF except serial interface and registers, which retain their values). A small RC lowpass filter can be used to minimize the effect of external digital noise. A logic-low on the SHDN pin overrides the serial bus SHDN bit status. Differential I-Channel Baseband Inputs to the Baseband Filter Differential Q-Channel Baseband Inputs to the Baseband Filter Leave Open Lock CMOS Output. This pin is an open-drain output. Output HIGH indicates the RF PLL is locked. Reference Frequency Input. This pin is internally biased to approximately +1.0V and must be ACcoupled to the reference source. This is a high-impedance port and can be externally terminated to the desired impedance. Supply for PLL. Bypass with a capacitor to GND (see the Typical Operating Circuit). Supply for Synthesizer Charge Pump. Bypass with a capacitor to GND (see the Typical Operating Circuit). RF Charge-Pump Output. Connect the RF PLL's loop filter between RFCP and system ground. Keep the line from this pin to the tank tune input as short as possible to prevent spurious pickup. Connect the loop filter as close to the tune input as possible. FUNCTION
3
VCC_PA
4
BIAS_SET
5
VGC
6
VCC_IF
7
VCC_BB
8
IDLE
9
SHDN
10, 11 12, 13 14, 24, 25 15 16 17 18
I+, IQ+, QN.C. LD REF VCC_PLL VCC_CP
19
RFCP
6
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WCDMA Quasi-Direct Modulator with VGA and PA Driver
Pin Description (continued)
PIN 20 21 22 23 26 27 28 -- NAME VCC_VCO GND_VCO VTUNE BYP CS SDATA SCLK EP FUNCTION Supply for VCO. Bypass to system ground with a capacitor as close to the pin as possible. Do not share ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). RF VCO Varactor Ground. Connect to the ground at the PLL loop-filter capacitors. Do not connect to the exposed pad. Oscillator-Frequency Tuning Voltage Input Bypass with a Capacitor to GND. The capacitor is used by the on-chip VCO voltage regulator (see the Typical Operating Circuit). 3-Wire Serial Bus Enable Input (Figure 1) 3-Wire Serial Bus Data Input (Figure 1) 3-Wire Serial Bus Clock Input (Figure 1) Exposed Pad. Connect to the ground plane for proper heat dissipation.
MAX2395
Detailed Description
The MAX2395 quasi-direct modulator accepts differential I/Q baseband inputs with external common-mode bias. A gain-control voltage pin (VGC) controls the gain of the IF and RF VGAs simultaneously to achieve the best current consumption and linearity performance.
Internal VCO and Tank
The integrated monolithic VCO and tank is tuned through the VTUNE pin. The RF/IF LO signals are generated from this oscillator.
PLL
The internal PLL uses a charge-pump output to drive a loop filter. The loop filter is typically a passive 2ndorder lead lag filter with a bandwidth of 10kHz. The loop filter must be optimized for a selected chargepump current, where KVCO = 90MHz/V. The internal architecture requires the RF VCO to run at 1.2x the desired frequency, mandating a 240kHz comparison frequency for an output step size of 200kHz. The LD output indicates whether the PLL is locked. An output high indicates a lock condition. There is an optional frequency doubler at the input of the PLL reference divider. When using a 13MHz reference frequency, either a 40kHz comparison can be used or the internal frequency doubler is enabled to allow a comparison frequency of 80kHz. The optional frequency double can be activated by setting OPCTRL register bit 7 = 1.
GmC Filters
The internal GmC filters are used to eliminate noise and baseband DAC aliasing signals above 8MHz. The GmC filter can be bypassed (GMC_EN bit, OPCTRL register bit 3), lowering the total current at the expense of no filtering. To speed up the settling time when transitioning from IDLE to transmit mode, the filter can be forced to stay active in IDLE mode using the IDLE_PRG bit (OPCTRL register bit 1). Contact factory if bypass mode is used.
I/Q Modulator
Differential in-phase (I) and quadrature-phase (Q) input pins are designed to be DC-coupled and biased with the baseband output from a digital-to-analog converter (DAC). The I_ and Q_ inputs need a DC bias, which can range from 1.35V to 1.65V. The current draw is negligible and the differential input capacitance is 4pF. The VCO frequency is divided by 6 to produce the RF I/Q LO signals.
PA Driver/RF Upconverter
The IF signal is upconverted with an image reject RF mixer, and differentially fed into the PA driver. The PA driver converts differential input signals to a singleended output. The driver requires a pullup inductor, which is part of the output matching network.
IF/RF VGA
The part offers approximately 90dB of gain-control range. An external voltage must be applied using a DAC allowing for dynamic gain control. To minimize the noise contribution from the DAC to the RF signal, place an RC filter at this pin (refer to the MAX2395 Evaluation Kit data sheet). The PA driver is included in the RF VGA.
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WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
Register Definition
The MAX2395 includes three programmable, 20-bit registers consisting of two divide registers and an operational control register. These registers are programmed from the SPI/ MICROWIRE-compatible serial port. The 4 least significant bits (LSBs) are reserved for the register's address. The register bits have been assigned to allow sharing of the 3-wire bus with the MAX2390/MAX2391/MAX2392/MAX2401 receiver ICs. The 16 most significant bits (MSBs) are used for register data. Data is shifted in MSB first, followed by the 4-bit address. When CS is low, the clock input is active and data is shifted with the rising edge of the clock. When CS transitions to high, the shift register is latched into the register selected by the contents of the address bits. Power-up defaults for the three registers are shown in Table 2. Initialize the registers according to the characterization table (Table 1). The RFM register sets the main frequency divide ratio for the RF PLL. The RFR register sets the reference frequency divide ratio. The RF VCO frequency is determined by the following: RF VCO frequency = fREFin (RFM/RFR) where fREFin is the external input reference frequency for the MAX2395. The operational control register (OPCTRL) controls the state of the IC. See Table 3 for the function of each bit. The RFR divide register includes test bits B9-B15. These bits are used to troubleshoot the VCO and synthesizer section (see Table 4). These bits are not needed for normal use and should be left as the values at power-up. The device offers several different operation modes for conserving power. Table 5 explains how to implement each mode.
Applications Information
External Matching to PA
The Tx outputs are internally matched to 50. The open-collector output requires a pullup inductor to VCC. The selection of matching in the MAX2395 Evaluation Kit allows optimization of ACPR.
Electromagnetic Compliance Considerations
Two major concepts should be employed to produce a low-spur and EMC-compliant transmitter: Minimize circular current-loop area to reduce H-field radiation, and minimize losses. To minimize circular current-loop area, bypass as close to the device as possible and use the distributed capacitance of a ground plane. To minimize losses, make RF traces short. Program only the necessary bits in any register to minimize clock cycles. RC filtering can also be used to slow the clock edges on the 3-wire interface, reducing highfrequency spectral content. RC filtering also provides for transient protection against IEC 802 testing by shunting high frequencies to ground, while the series resistance attenuates the transients for error-free operation. The same applies to the logic-input pins (SHDN, IDLE). High-frequency bypass capacitors are required close to the pins with a dedicated via to ground. The package provides minimal inductance ground by using an exposed pad under the part. Provide at least five lowinductance vias under the pad to ground to minimize ground inductance. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as a slot radiator and reduce its shield effectiveness.
Layout Issues
The MAX2395 Evaluation Kit can be used as a reference for board layout. Gerber files are available upon request at www.maxim-ic.com. To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate VCC node in the circuit. At the end of each trace is a bypass capacitor with impedance to ground less than 1 at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor.
Shutdown and Idle ModeTM
The part offers a shutdown mode and idle mode for optimal power management. In shutdown mode, all functions are turned off except the serial interface. When the part is shut down using the OPCTRL register, the IC draws a residual current of 60A (typ). In idle mode, the VCO, PLL, and serial interface remain on to minimize startup time. The GmC filter can be software programmed to power on or off during idle mode (see Table 5).
Idle Mode is a trademark of Maxim Integrated Products, Inc.
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WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
Table 2. Register Power-Up Default States (fREF = 19.2MHz, fRF = 1950MHz)
REGISTER RFM RFR OPCTRL DEFAULT 9750 dec 4050 hex (80 dec for /R) 197D hex ADDRESS 0010b 0000b 0100b FUNCTION Main-divider ratio register Reference-divider register Operational control settings
Table 3. Operation Control Register (OPCTRL) Bit Assignments
BIT NAME POWER-UP STATE BIT LOCATION (0 = LSB) FUNCTION
SHDN
1
0
Setting this bit to zero shuts down everything except the serial interface and registers, which retain their values. It is overridden by a logic-low on the SHDN pin. If bit is set to 1, this leaves the GmC filters and the servo loop ON when the IDLE pin goes LOW. If bit is set to zero, the GmC filters shut off when the IDLE pin goes LOW. Leave in power-up state. Setting this bit to zero bypasses GmC filters. Setting this bit to zero shuts off the RF PLL. Setting this bit to zero shuts off the RF VCO. Setting this bit to zero shuts off the PA driver, RF upconverter, and IF modulator sections. Setting this bit to 1 enables the X2 multiplier for use in the REF divider section when TCXO frequency is 13MHz. Maximum power level setting: 1 = +6dBm; 0 = +3dBm Predriver bias: 0 = -25%; 1 = nominal Output bias: 0 = nominal; 1 = +30% A 2-bit word sets the RF charge-pump current as follows: 0 0 = 1000A 0 1 = 1500A 1 0 = 2000A 1 1 = 2500A A 2-bit word sets the Ameliorator current as follows: 0 0 = Off 0 1 = Low (nominal) 1 0 = Mid 1 1 = High These bits are used in DC offset trimming mode, where DC_TRM = 1. Setting this bit to 1 enables the DC offset trimming mode.
IDLE_PRG -- GmC_EN PLL_EN VCO_EN PA_RF_IF_EN X2_EN MPL PRD_Bias OUT_Bias
0 1 1 1 1 1 0 1 0 0
1 2 3 4 5 6 7 8 9 10
RCP1, RCP0
11
12, 11
AML1, AML0
00
14, 13
DC_TRM
0
15
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WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
Table 4. Reference-Divider (RFR) Register
BIT NAME RFR8 to RFR0 POWER-UP STATE 001010000 BIT LOCATION (0 = LSB) 8 to 0 FUNCTION Reference-divider register bits 0 0 = Normal operation (lock-detect output at LD pin) 0 1 = RFM-DIV output 1 0 = RFR-DIV output 1 1 = Low logic output RF CP test bits: 0 0 0 = Normal mode 0 0 1 = Source sink ON 0 1 1 = Sink ON 1 0 1 = Source ON 1 1 0 = Source, sink OFF Program to 1 for normal operation Program to 0 for normal operation
LD1, LD0
00
10, 9
RCPT2, RCPT1, RCPT0
000
13, 12, 11
RESERVED RESERVED
1 0
14 15
Table 5. Power-Down Modes
I/Q MOD, RF UC, PA DRIVER IDLE_PRG BIT (1)
SHDN PIN (9)
SHDN BIT (0)
SERIAL BUS
IDLE PIN (8)
RF VCO
RF PLL
POWER-DOWN MODES
COMMENTS
0 1 1
X 0 1
X X 0
X SHDN mode X 0 IDLE mode
All OFF except serial bus and registers (which retain values). A zero on the SHDN pin overrides the SHDN bit. All OFF except RF PLL, RF VCO, serial bus, and registers (which retain values). RF PLL and RF VCO are on or off depending on the control-bit values before toggling the IDLE pin to zero. The 5 different TX blocks can be toggled ON/OFF using the serial bus.
OFF OFF ON ON OFF X X OFF OFF OFF OFF
1
1
0
1
ON
OFF
X
X
1
1
1
X
Power-up mode
ON
X
X
X
10
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GmC X X
WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
SDATA BIT 15 BIT 14 BIT 5 BIT 4 A1 A0
SCLK tCWH CS tCWL
tCS
tCH
tES
Figure 1. 3-Wire SPI/MICROWIRE Serial-Interface Timing Diagram
MSB B15 B14 B13 B12 B11 B10 B9 DATA 16 BITS B8 B7
20-BIT REGISTER B6 B5 B4 B3 B2 B1 B0 A3 ADDRESS 4 BITS A2 A1 ADDRESS 0 1
LSB A0
B15
B14
B13
B12
B11
B10
RFM DIVIDE RATIO REGISTER (16 BITS) B9 B8 B7 B6 B5
B4
B3
B2
B1
B0
0
0
B15
B14
B13
B12
B11
B10
B9
B8
B7
RFR DIVIDE RATIO REGISTER (9 BITS) B6 B5 B4 B3 B2
B1
B0
0
ADDRESS 0 0 ADDRESS 1 0
0
B15
B14
B13
B12
B11
OPERATION CONTROL REGISTER (16 BITS) B10 B9 B8 B7 B6 B5
B4
B3
B2
B1
B0
0
0
Figure 2. Register Assignments
It is recommended that the exposed pad be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. Soldering the pad to ground is critical for proper heat dissipation. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as a slot radiator and reduce its shield effectiveness.
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WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395
Typical Operating Circuit
TCXO 19.2MHz
SDATA
SCLK
VCC
CS
N.C.
N.C.
BVP
23 22
VTUNE
28 1 2 3 4 5 6
27 SERIAL BUS
26
25
24
VCC
N.C. POWER AMPLIFIER POUT VCC _PA BIAS_SET
21 20 RF INTEGER-N PLL 19 18 17
GND_VCO
100pF
VCC _VCO RFCP VCC _CP VCC _PLL REF LD
LO GEN
VGC VCC _IF VCC _BB
0
90
MAX2395 16
7 8 9 10 11 12 13 14
15
100pF IDLE SHDN N.C. I+ IQ+ Q-
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 28 QFN-EP 28 TQFN-EP PACKAGE CODE G2855-2 T2855-3 DOCUMENT NO. 21-0091 21-0140
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WCDMA MODEM
WCDMA Quasi-Direct Modulator with VGA and PA Driver
Revision History
REVISION NUMBER 2 3 REVISION DATE 5/05 1/09 -- Removed obsolete parts MAX2394/MAX2403/MAX2407 from data sheet DESCRIPTION PAGES CHANGED -- 1-13
MAX2395
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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